IBIS Macromodel Task Group

Meeting date: 23 February 2021

Members (asterisk for those attending):
Achronix Semiconductor      * Hansel Dsilva
ANSYS:                      * Curtis Clark
                            * Wei-hsing Huang
Cadence Design Systems:     * Ambrish Varma
                              Ken Willis
                            * Jared James
Google:                     * Zhiping Yang
Intel:                      * Michael Mirmak
                              Kinger Cai
                              Alaeddin Aydiner
Keysight Technologies:      * Fangyi Rao
                            * Radek Biernacki
                            * Ming Yan
                            * Todd Bermensolo
                              Rui Yang
Luminous Computing            David Banas
Marvell                       Steve Parker
Mentor, A Siemens Business: * Arpad Muranyi
Micron Technology:          * Randy Wolff
                              Justin Butterfield
Missouri S&T                * Chulsoon Hwang
SAE ITC                       Jose Godoy
SiSoft (Mathworks):         * Walter Katz
                              Mike LaBonte
Teraspeed Labs:             * Bob Ross
Zuken USA:                  * Lance Wang

The meeting was led by Arpad Muranyi.  Curtis Clark took the minutes.

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Opens:
  
- Professor Chulsoon Hwang from MS&T introduced himself.  He and his students
are interested in IBIS modeling from an academic perspective, and they have been
working with Zhiping Yang on ways to improve PSIJ (power supply induced jitter)
modeling in IBIS.

- Michael Mirmak noted that the Interconnect task group has been suspended now
that BIRD202.2 has been submitted.  The Editorial task group, which had been
suspended, will be restarting to work on existing IBIS 7.0 issues and start
considering IBIS 7.1 content soon.  The meetings will take placed on Fridays at
9AM PST on the weeks when the Open Forum meeting does not meet.  The meeting
will use the Open Forum meeting connection details.  Arpad noted that anyone
interested in the editorial process can join.

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Review of ARs:

- Arpad and Ambrish to suggest a better name for Use_New_Flow.
  - Done.  Arpad reported that he had proposed a name to Fangyi before Fangyi
    submitted BIRD210.

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Call for patent disclosure:

- None.

-------------------------
Review of Meeting Minutes:

Arpad asked for any comments or corrections to the minutes of the February 16th
meeting.  Michael moved to approve the minutes.  Randy seconded the motion.
There were no objections.

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New Discussion:

Redriver Flow Issues:
Arpad reported that Fangyi had submitted BIRD210, and at the last Open Forum
meeting a motion to send it back to ATM for further discussion had been
approved.  Arpad said this was on the agenda as item #7.

PSIJ modeling in IBIS:
Chulsoon Hwang shared the presentation "Improving Power Supply Induced Jitter
Simulation Accuracy".  He noted that this presentation was modified and updated,
but the work had originally been presented at the EMC+SIPI IBIS virtual summit
in 2020.  Chulsoon said they were bringing it to ATM for further review and
comments prior to drafting a BIRD.

slide 3: Power Supply Induced Jitter (PSIJ)
PSIJ is jitter induced in the signal by variations in the power supply.

slide 4: Limitations of IBIS Models
Most PSIJ is caused by internal buffer delay not the last stage buffer.  Current
IBIS power-aware models cannot capture this effect.

slide 5: Power-Aware IBIS Model
Power-aware IBIS models using the gate modulation coefficients Ksspu and Ksspd
provide a multiplier scaling of Ku(t) and Kd(t) based on power rail voltages.
Therefore, they can affect slew rates and DC levels but cannot model changes in
the location of the edge due to power rail noise.

Chulsoon said Ksspd and Ksspu information is extracted from I-V data at the last
stage buffer, so it can't take delay changes into account.  Their motivation in
this work is to include this jitter effect in IBIS models.

slide 6: PSIJ Mechanism
This slide presents a figure and function describing the instantaneous timing
variation in terms of the power supply rejection ratio (PSRR) and the
accumulation of this timing variation during the propagation delay through the
buffer.  Chulsoon said the key idea in this work is that we need to aggregate
these instantaneous effects during the propagation delay through the buffer.
The signal is affected by the power supply noise throughout the propagation
delay, so we need to take the time average of the power rail voltage.

There are three important terms in this:
- Jitter sensitivity at DC
  - IBIS models can capture this in the propagation delay variations between
    typ/min/max waveforms.
- Frequency dependency due to PSRR
  - Assuming frequency invariance here (limitation)
- Time averaged power noise
  - This work introduces this time averaged noise into Ku(t) and Kd(t) scalers.

slide 7: Ku(t) and Kd(t) Modification example.
This work proposes that the Ku(t) and Kd(t) scalers be augmented with two new
additive terms with time varying coefficients.  These terms are linear and
second order functions of the time averaged power rail voltage Vcc(t).

slide 8: Coefficient Extraction
The coefficients of the new terms, Bu(t) and Au(t), can be derived using the
familiar two equations and two unknowns approach.  This time it is based on the
legacy Ku(t) and Kd(t) waveforms for the typ/min/max variations.  (similarly
for the Bd(t) and Ad(t) terms).

slide 9-11: Validation cases
These slides show good agreement between a test implementation of this algorithm
and a full SPICE simulation.  The edge shift effects were properly captured for
an example with DC power supply level shifts, an example with voltage supply
noise that is low frequency relative to the propagation delay, and an example
with voltage supply noise that is high frequency relative to the propagation
delay (no shift observed).

slide 12: BIRD
The key issue is how to include propagation delay typ/min/max variations.
- Include a specific and meaningful time 0 in rising/falling waveforms.
- BIRD68.1 had proposed a common timing reference for all waveforms, but it
  didn't state where the reference point should be set.
- Randy Wolff had pointed out that we would need a way to tell model extraction
  software to start all waveform tables at a specific time aligned with a time
  reference inside the SPICE subcircuit.  It might cause problems for existing
  model creation software.
- We want to provide a list of delay values over typ/min/max variations.  Should
  we use the [Initial Delay] or a new keyword?

Michael asked if this was strictly for traditional IBIS.  It's for modeling the
impact of voltage supply variations on timing analysis, and it's not meant to
interact with AMI?  Chulsoon agreed that it was not intended for AMI.  Michael
said he just wanted to make sure we were careful to consider how any new
keywords might interact with AMI simulations.  Zhiping said he wasn't aware of
AMI simulations using PSIJ and asked if Michael knew if/how anyone had done it.
Michael said they occasionally get questions on how effects from the analog
side of the buffer could get incorporated into an AMI model.  For example, if
you have a sophisticated modeling of effects in the timing model, how do you
represent them if you want to put an algorithmic modeling block on top of it?
Arpad said the challenge with AMI modeling is that it assumes the analog and
channel portions are LTI.  These types of jitter like PSIJ are time-varying
effects that violate that assumption.  Wei-hsing said that when the signal is
differential this psij effect is diminished, and differential had been the
typical domain of AMI until recently.  Arpad recalled that Ted Mido had
presented a paper at a Japan IBIS Summit (2018), and he had worked on
characterizing PSIJ effects and capturing them in AMI jitter parameters.  Arpad
said it might be helpful to review that presentation.

Arpad asked about the PSRR that appeared in slide 6 but not in the equations
on slide 7.  Chulsoon said the PSRR' (prime) on slide 6 referred to a
normalized PSRR, and given the assumption that PSRR is frequency invariant,
it was folded directly into term 1 on slide 6.

Fangyi asked what the Tswitch term in the equations on slide 7 meant.  Chulsoon
said the integration for computing the time averaged value of Vcc(t) is over
the propagation delay.  Arpad asked if this is the internal buffer delay.
Chulsoon said it's the time from the input switching to the output getting to
the halfway point of the transition.  Fangyi said this would be problematic,
because the simulator is solving for Vcc(t) at simulation time, but this
formulation in the IBIS model would be asking the simulator to compute an
integral over Tswitch before t had gotten that far.  It would be a non-causal
situation asking the simulator to solve at time t by performing an integration
that relies on a future time.  (Note: Chulsoon said after the meeting that the
Tswitch and his answer to Fangyi's question had caused confusion.  The intent is
not to integrate over a fixed interval or cause a non-causal situation.
Chulsoon will clarify this point at the next meeting).

Arpad noted Randy's comment on the last slide about timing references.  He said
his recollection was that the Rising and Falling waveforms should have the same
t=0 reference, but that there was no requirement in the existing specification
that the t=0 reference is the same across typ/min/max variations.  He said if
these derivations rely on timing variations between typ/min/max variants, then
he agreed with Randy that we need to find a good way to make that reference
available or these equations might not work.  Randy said that you also have
process and temperature, not just voltage, variations represented in the
typ/min/max, so trying to just separate the voltage effects would be an issue.
We might want a new keyword to just deliver the information we need.  Arpad said
he'd raised the point because it's likely old models won't work with this new
formulation since we can't rely on a common t=0, particularly if model makers
had shifted their typ/min/max waveforms around to avoid the over-clocking issue.
This would only work for new models with carefully extracted sets of waveforms.

Bob said the [Initial Delay] keyword has typ/min/max values.  Arpad said that's
used when people chop off the initial portions of their V-T waveforms.  That
information is then contained in the [Initial Delay] keyword.  Arpad said one
other issue was how much of the pre-driver inverter chain was included in the
extraction.  You could conceivably extract typ/min/max waveforms without this
effect included if the extraction didn't include the pre-driver stages.  Bob
said you might be able to assume the predriver impact should be the same for
typ/min/max, or as a practical matter maybe you could remove different delays
from typ vs. min vs. max.

Bob asked a question about slide 9, the DC supply level(s) validation case.  He
noted that the load at the Vout location was just a nominal capacitance.  If the
correlation tests were done with a 50 Ohm load to ground or a 50 Ohm load to
Vcc, how well would they correlate with SPICE?  Chulsoon said he would
investigate to see how well things correlated under those loads.  He said he
expected the underlying mechanism wouldn't change and the correlation would be
good.  Arpad said this was a good example to test, since transmission lines tend
to look like resistive loads, at least until the reflections come back.

Fangyi asked if the propagation delay mentioned in item two of slide 12 was
voltage dependent.  Chulsoon said yes, he was envisioning providing three delay
values in typ/min/max corners that correspond to the Voltage Range keyword's
typ/min/max voltages.  This would provide propagation delays for the DC voltage
cases (typ/min/max), and the tool would be responsible for extending that to the
AC power supply variations.

Randy asked if the effect couldn't be distilled into one value with units like
ps/mV to explain the effect of power supply voltage variation on propagation
delay.  Chulsoon said you would still need to get the time average voltage noise
over the propagation delay.  Walter said the numbers he would be interested in
are something you might measure in a lab.  For example, inject a 5mV sinusoidal
voltage noise and measure how that relates to sinusoidal jitter.  Chulsoon said
you would have to do that at all frequencies you care about.  Walter said his
understanding was that power supply noise is pretty low frequency, for example,
around 200MHz.  Chulsoon said the upper bounds of the frequency range would be
defined by the propagation delay.

Arpad asked if this discussion had given Chulsoon what he needed.  Chulsoon said
he was happy to discuss it further.  Ming asked if Chulsoon could provide more
details on how any proposed new parameters might work and what they would look
like in the specification.  Zhiping suggested Chulsoon could send his submitted
paper on this topic to the ATM group as well, and he asked people to remember
this paper is not yet published.  Chulsoon agreed.

- Randy: Motion to adjourn.
- Zhiping: Second.
- Arpad: Thank you all for joining.

AR: Chulsoon to send his presentation and upcoming paper on PSIJ to the ATM
    list.

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Next meeting: 02 March 2021 12:00pm PT
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IBIS Interconnect SPICE Wish List:

1) Simulator directives
